Instruction Set

The Complete Pentium Instruction Set Table (32 Bit Addressing Mode Only)

Source : http://gynvael.vexillium.org/dump/opcodes.txt (by Sang Cho)

Explanation of the Notation used in this Table

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NotationExplanation
/digitA digit between 0 and 7 indicates that the ModR/M byte of the instruction uses only the r/m (register or memory) operand. The reg field contains the digit that provides an extension to the instruction’s opcode.
/rIndicates that the ModR/M byte of the instruction contains both a register operand and an r/m operand.
cbA relative byte offset from the next instruction for JMP, CALL etc.
cwA relative word offset from the next instruciton for JMP, CALL etc.
cd– A relative doubleword offset from the next instruction for JMP, CALL etc.
cp– An absolute far pointer for JMP, CALL etc.
ib, iw, id– 1-byte (ib), 2-byte (iw), or 4-byte (id) immediate operand
+rb, +rw, +rd– register code, from 0 through 7, added to an opcode byte.
rb rw rd
———————-
AL = 0 AX = 0 EAX = 0
CL = 1 CX = 1 ECX = 1
DL = 2 DX = 2 EDX = 2
BL = 3 BX = 3 EBX = 3
AH = 4 SP = 4 ESP = 4
CH = 5 BP = 5 EBP = 5
DH = 6 SI = 6 ESI = 6
BH = 7 DI = 7 EDI = 7
NotationExplanation
+i– A number used in floating-point instructions when one of the operands is ST(i) from the FPU register stack.
rel8– A relative address in the range from -128 to 127 bytes from the end of the instruction.
rel16 and rel32– A relative address within the same code segment as the instruction assembled.
ptr16:16 and ptr16:32– A far pointer, typically in a code segment different from that of the instruction.
r8– One of the byte general-purpose registers.
r16– One of the word general-purpose registers.
r32– One of the doubleword general-purpose registers.
imm8– An immediate byte value.
imm16– An immediate word value.
imm32– An immediate doubleword value.
r/m8– A byte general-purpose register, or a byte from memory.
r/m16– A word general-purpose register, or a word memory operand.
r/m32– A doubleword general-purpose register, or a doubleword memory operand.
m– A 16- or 32-bit operand in memory.
m8– A byte operand in memory, pointed to by the DS:(E)SI or ES:(E)DI registers. Used with the string instructions nd the XLAT instruction.
m16– A word operand in memory, pointed to by the DS:(E)SI or ES:(E)DI registers. Used only with the string instructions.
m32– A doubleword operand in memory, pointed to by the DS:(E)SI or ES:(E)DI registers. Used only with the string instructions.
m64– A memory quadword operand in memory. Used only with the CMPXCHG8B instruction.
m16:16, m16:32– A memory operand containing a far pointer composed of two numbers. The number to the left of the colon corresponds to the pointer’s segment selector. The number to the right corresponds to its offset.
m16&32, m16&16, m32&32– A memory operand consisting of data item pairs whose sizes are indicated on the left and the right side of the ampersand. All memory addressing modes are allowed. The m16&16 and m32&32 operands are used by the BOUND instruction to provide an operand containing an upper and lower bounds for array indices. The m16&32 operand is used by LIDT and LGDT to provide a word with which to load the limit field, and a doubleword with which to load the base field of the corresponding GDTR and IDTR registers.
moffs8, moffs16, moffs32– A simple memory variable (memory offset) of type byte, word, or doubleword used by some variants of the MOV instruction. The actual address is given by a simple offset relative to the segment base. No ModR/M byte is used in the instruction. The number shown with moffs indicates its size, which is determined by the address-size attribute of the instruction.
Sreg– A segment register. The segment register bit assignments are ES=0, CS=1, SS=2, DS=3, FS=4, and GS=5.
m32real, m64real, m80real- A single-, double-, and extended-real floating-point operand in memory.
m16int, m32int, m64int– A word-, short-, and long-integer floating-point operand in memory.
ST or ST(0)– The top element of the FPU register stack.
ST(i)– The i th element from the top of the FPU register stack. (i = 0 through 7)
mm– An MMX register. The 64-bit MMX registers are: MM0 through MM7.
mm/m32– The low order 32 bits of an MMX register or a 32-bit memory operand.
mm/m64– An MMX register or a 64-bit memory operand.
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Alphabetical Listing

Opcode,DataInstructionExplanation
37AAAASCII adjust AL after addition
D5 0AAADASCII adjust AX before division
D4 0AAAMASCII adjust AX after multiplication
3FAASASCII adjust AL after subtraction
14 ibADC AL,imm8Add with carry
15 idADC EAX,imm32Add with carry
80 /2 ibADC r/m8,imm8Add with carry
81 /2 idADC r/m32,imm32Add with carry
83 /2 ibADC r/m32,imm8Add with carry
10 /rADC r/m8,r8Add with carry
11 /rADC r/m32,r32Add with carry
12 /rADC r8,r/m8Add with carry
13 /rADC r32,r/m32Add with carry
04 ibADD AL,imm8Add
05 idADD EAX,imm32Add
80 /0 ibADD r/m8,imm8Add
81 /0 idADD r/m32,imm32Add
83 /0 ibADD r/m32,imm8Add
00 /rADD r/m8,r8ADD
01 /rADD r/m32,r32ADD
02 /rADD r8,r/m8ADD
03 /rADD r32,r/m32ADD
24 ibAND AL,imm8AND
25 idAND EAX,imm32AND
80 /4 ibAND r/m8,imm8AND
81 /4 idAND r/m32,imm32AND
83 /4 ibAND r/m32,imm8AND
20 /rAND r/m8,r8AND
21 /rAND r/m32,r32AND
22 /rAND r8,r/m8AND
23 /rAND r32,r/m32AND
63 /rARPL r/m16,r16Adjust Request Privilege Level of Sel.
62 /rBOUND r32,m32&32Check Array Index Against Bounds
0F BC /rBSF r32,r/m32Bit scan forward on r/m32
0F BD /rBSR r32,r/m32Bit scan reverse on r/m32
0F C8+rdBSWAP r32Reverses the byte order of a r32
0F A3 /rBT r/m32,r32Bit Test
0F BA /4 ibBT r/m32,imm8Bit Test
0F BB /rBTC r/m32,r32Bit Test and Complement
0F BA /7 ibBTC r/m32,imm8Bit Test and Complement
0F B3 /rBTR r/m32,r32Bit Test and Clear
0F BA /6 ibBTR r/m32,imm8Bit Test and Clear
0F AB /rBTS r/m32,r32Bit Test and Set
0F BA /5 ibBTS r/m32,imm8Bit Test and Set
E8 cdCALL rel32Call near, rel to n.inst
FF /2CALL r/m32Call near, abs.ind.add. given in r/m32
9A cpCALL ptr16:32Call far, abs.add. given in operand
FF /3CALL m16:32Call far, abs.ind.add. given in m16:32
98CBWConvert Byte to Word
99CWDConvert Word to Doubleword
99CDQConvert Doubleword to Quadword
F8CLCClear CF flag
FCCLDClear DF flag
FACLIClear interrupt flag
0F 06CLTSClear Task-Switched Flag in Control Reg. Zero
F5CMCComplement CF flag
0F 47 /rCMOVA r32,r/m32Move if above
0F 43 /rCMOVAE r32,r/m32Move if above or equal
0F 42 /rCMOVB r32,r/m32Move if below
0F 46 /rCMOVBE r32,r/m32Move if below or equal
0F 42 /rCMOVC r32,r/m32Move if carry
0F 44 /rCMOVE r32,r/m32Move if equal
0F 4F /rCMOVG r32,r/m32Move if greater
0F 4D /rCMOVGE r32,r/m32Move if greater or equal
0F 4C /rCMOVL r32,r/m32Move if less
0F 4E /rCMOVLE r32,r/m32Move if less or equal
0F 46 /rCMOVNA r32,r/m32Move if not above
0F 42 /rCMOVNAE r32,r/m32Move if not above or equal
0F 43 /rCMOVNB r32,r/m32Move if not below
0F 47 /rCMOVNBE r32,r/m32Move if not below or equal
0F 43 /rCMOVNC r32,r/m32Move if not carry
0F 45 /rCMOVNE r32,r/m32Move if not equal
0F 4E /rCMOVNG r32,r/m32Move if not greater
0F 4C /rCMOVNGE r32,r/m32Move if not greater or equal
0F 4D /rCMOVNL r32,r/m32Move if not less
0F 4F /rCMOVNLE r32,r/m32Move if not less or equal
0F 41 /rCMOVNO r32,r/m32Move if not overflow
0F 4B /rCMOVNP r32,r/m32Move if not parity
0F 49 /rCMOVNS r32,r/m32Move if not sign
0F 45 /rCMOVNZ r32,r/m32Move if not zero
0F 40 /rCMOVO r32,r/m32Move if overflow
0F 4A /rCMOVP r32,r/m32Move if parity
0F 4A /rCMOVPE r32,r/m32Move if parity even
0F 4B /rCMOVPO r32,r/m32Move if parity odd
0F 48 /rCMOVS r32,r/m32Move if sign
0F 44 /rCMOVZ r32,r/m32Move if zero
3C ibCMP AL,imm8Compare
3D idCMP EAX,imm32Compare
80 /7 ibCMP r/m8,imm8Compare
81 /7 idCMP r/m32,imm32Compare
83 /7 ibCMP r/m32,imm8Compare
38 /rCMP r/m8,r8Compare
39 /rCMP r/m32,r32Compare
3A /rCMP r8,r/m8Compare
3B /rCMP r32,r/m32Compare
A6CMPSBCompare byte at DS:(E)SI with ES:(E)DI
A7CMPSDCompare dw at DS:(E)SI with ES:(E)DI
0F B0 /rCMPXCHG r/m8,r8Compare and Exchange
0F B1 /rCMPXCHG r/m32,r32Compare and Exchange
0F C7 /1 m64CMPXCHG8B m64Compare and Exchange
0F A2CPUIDEAX := Processor id.info.
27DAADecimal adjust AL after addition
2FDASDecimal adjust AL after subtraction
FE /1DEC r/m8Decrement r/m8 by 1
FF /1DEC r/m32Decrement r/m32 by 1
48+rdDEC r32Decrement r32 by 1
F6 /6DIV r/m8Unsigned divide AX by r/m8
F7 /6DIV r/m16Unsigned divide DX:AX by r/m16
F7 /6DIV r/m32Unsigned divide EDX:EAX by r/m32
0F 77EMMSSet the FP tag word to empty
C8 iw 00ENTER imm16,0Create a stack frame for a procedure
C8 iw 01ENTER imm16,1Create a nested stack frame for a proc.
C8 iw ibENTER imm16,imm8Create a nested stack frame for a proc.
D9 F0F2XM1Replace ST(0) with 2**ST(0) - 1
D9 E1FABSReplace ST(0) with its absolute value
D8 /0FADD m32realAdd m32real to ST(0) and s.r. in ST(0)
DC /0FADD m64realAdd m64real to ST(0) and s.r.in ST(0)
D8 C0+iFADD ST(0),ST(i)Add ST(0) to ST(i) and s.r.in ST(0)
DC C0+iFADD ST(i),ST(0)Add ST(i) to ST(0) and s.r. in ST(i)
DE C0+iFADDP ST(i),ST(0)Add ST(0) to ST(i), s.r.in ST(i),pop r.stack
DE C1FADDPAdd ST(0) to ST(1), s.r.in ST(1),pop r.stack
DA /0FIADD m32intAdd m32int to ST(0) and s.r.in ST(0)
DE /0FIADD m16intAdd m16int to ST(0) and s.r.in ST(0)
DF /4FBLD m80bcdConvert m80BCD to real and push
DF /6FBSTP m80bcdStore ST(0) in m80bcd and pop ST(0)
D9 E0FCHSComplements sign of ST(0)
9B DB E2FCLEXClear f.e.f. after checking for ..
DB E2FNCLEXClear f.e.f. without checking for ..
DA C0+iFCMOVB ST(0),ST(i)Move if below
DA C8+iFCMOVE ST(0),ST(i)Move if equal
DA D0+iFCMOVBE ST(0),ST(i)Move if below or equal
DA D8+iFCMOVU ST(0),ST(i)Move if unordered
DB C0+iFCMOVNB ST(0),ST(i)Move if not below
DB C8+iFCMOVNE ST(0),ST(i)Move if not equal
DB D0+iFCMOVNBE ST(0),ST(i)Move if not below or equal
DB D8+iFCMOVNU ST(0),ST(i)Move if not unordered
D8 /2FCOM m32realCompare ST(0) with m32real.
DC /2FCOM m64realCompare ST(0) with m64real.
D8 D0+iFCOM ST(i)Compare ST(0) with ST(i).
D8 D1FCOMCompare ST(0) with ST(1).
D8 /3FCOMP m32realCompare ST(0) with m32real,pop r.stack.
DC /3FCOMP m64realCompare ST(0) with m64real,pop r.stack.
D8 D8+iFCOMP ST(i)Compare ST(0) with ST(i), pop
D8 D9FCOMPCompare ST(0) with ST(1), pop
DE D9FCOMPPCompare ST(0) with ST(1), pop pop
DB F0+iFCOMI ST,ST(i)Compare ST(0) with ST(i), set status flags
DF F0+iFCOMIP ST,ST(i)Compare ST(0) with ST(i), set s.f. ,pop
DB E8+iFUCOMI ST,ST(i)Compare ST(0) with ST(i), check o.v.set s.f.
DF E8+iFUCOMIP ST,ST(i)Compare ST(0) with ST(i), check ovssf pop
D9 FFFCOSReplace ST(0) with its cosine
D9 F6FDECSTPDecrement TOP field in FPU status word.
D8 /6FDIV m32realDivide ST(0) by m32real and s.r.in ST(0)
DC /6FDIV m64realDivide ST(0) by m64real and s.r.in ST(0)
D8 F0+iFDIV ST(0),ST(i)Divide ST(0) by ST(i) and s.r.in ST(0)
DC F8+iFDIV ST(i),ST(0)Divide ST(i) by ST(0) and s.r.in ST(i)
DE F8+iFDIVP ST(i),ST(0)Divide ST(i) by ST(0), s.r.in ST(i) pop
DE F9FDIVPDivide ST(1) by ST(0), s.r.in ST(1) pop
DA /6FIDIV m32intDivide ST(0) by m32int and s.r.in ST(0)
DE /6FIDIV m16intDivide ST(0) by m64int and s.r.in ST(0)
D8 /7FDIVR m32realDivide m32real by ST(0) and s.r.in ST(0)
DC /7FDIVR m64realDivide m64real by ST(0) and s.r.in ST(0)
D8 F8+iFDIVR ST(0),ST(i)Divide ST(i) by ST(0) and s.r.in ST(0)
DC F0+iFDIVR ST(i),ST(0)Divide ST(0) by ST(i) and s.r.in ST(i)
DE F0+iFDIVRP ST(i),ST(0)Divide ST(0) by ST(i), s.r.in ST(i) pop
DE F1FDIVRPDivide ST(0) by ST(1), s.r.in ST(1) pop
DA /7FIDIVR m32intDivide m32int by ST(0) and s.r.in ST(0)
DE /7FIDIVR m16intDivide m64int by ST(0) and s.r.in ST(0)
DD C0+iFFREE ST(i)Sets tag for ST(i) to empty
DE /2FICOM m16intCompare ST(0) with m16int
DA /2FICOM m32intCompare ST(0) with m32int
DE /3FICOMP m16intCompare ST(0) with m16int and pop
DA /3FICOMP m32intCompare ST(0) with m32int and pop
DF /0FILD m16intPush m16int
DB /0FILD m32intPush m32int
DF /5FILD m64intPush m64int
D9 F7FINCSTPIncrement the TOP field FPU status r.
9B DB E3FINITInitialize FPU after …
DB E3FNINITInitialize FPU without …
DF /2FIST m16intStore ST(0) in m16int
DB /2FIST m32intStore ST(0) in m32int
DF /3FISTP m16intStore ST(0) in m16int and pop
DB /3FISTP m32intStore ST(0) in m32int and pop
DF /7FISTP m64intStore ST(0) in m64int and pop
D9 /0FLD m32realPush m32real
DD /0FLD m64realPush m64real
DB /5FLD m80realPush m80real
D9 C0+iFLD ST(i)Push ST(i)
D9 E8FLD1Push +1.0
D9 E9FLDL2TPush log2 10
D9 EAFLDL2EPush log2 e
D9 EBFLDPIPush pi
D9 ECFLDLG2Push log10 2
D9 EDFLDLN2Push loge 2
D9 EEFLDZPush +0.0
D9 /5FLDCW m2byteLoad FPU control word from m2byte
D9 /4FLDENV m14/28byteLoad FPU environment from m14/m28
D8 /1FMUL m32realMultiply ST(0) by m32real and s.r.in ST(0)
DC /1FMUL m64realMultiply ST(0) by m64real and s.r.in ST(0)
D8 C8+iFMUL ST(0),ST(i)Multiply ST(0) by ST(i) and s.r.in ST(0)
DC C8+iFMUL ST(i),ST(0)Multiply ST(i) by ST(0) and s.r.in ST(i)
DE C8+iFMULP ST(i),ST(0)Multiply ST(i) by ST(0), s.r.in ST(i) pop
DE C9FMULPMultiply ST(1) by ST(0), s.r.in ST(1) pop
DA /1FIMUL m32intMultiply ST(0) by m32int and s.r.in ST(0)
DE /1FIMUL m16intMultiply ST(0) by m16int and s.r.in ST(0)
D9 D0FNOPNo operation is performed
D9 F3FPATANRepalces ST(1) with arctan(ST(1)/ST(0)) pop
D9 F8FPREMReplaces ST(0) with rem (ST(0)/ST(1))
D9 F5FPREM1Replaces ST(0) with IEEE rem(ST(0)/ST(1))
D9 F2FPTANReplaces ST(0) with its tangent push 1.0
D9 FCFRNDINTRound ST(0) to an integer
DD /4FRSTOR m94/108byteLoad FPU status from m94 or m108 byte
9B DD /6FSAVE m94/108byteStore FPU status to m94 or m108
DD /6FNSAVE m94/108byteStore FPU environment to m94 or m108
D9 FDFSCALEScale ST(0) by ST(1)
D9 FEFSINReplace ST(0) with its sine
D9 FBFSINCOSCompute sine and consine of ST(0) s push c
D9 FAFSQRTsquare root of ST(0)
D9 /2FST m32realCopy ST(0) to m32real
DD /2FST m64realCopy ST(0) to m64real
DD D0+iFST ST(i)Copy ST(0) to ST(i)
D9 /3FSTP m32realCopy ST(0) to m32real and pop
DD /3FSTP m64realCopy ST(0) to m64real and pop
DB /7FSTP m80realCopy ST(0) to m80real and pop
DD D8+iFSTP ST(i)Copy ST(0) to ST(i) and pop
9B D9 /7FSTCW m2byteStore FPU control word
D9 /7FNSTCW m2byteStore FPU control word without
9B D9 /6FSTENV m14/28byteStore FPU environment
D9 /6FNSTENV m14/28byteStore FPU env without
9B DD /7FSTSW m2byteStore FPU status word at m2byte after
9B DF E0FSTSW AXStore FPU status word in AX after
DD /7FNSTSW m2byteStore FPU status word at m2byte without
DF E0FNSTSW AXStore FPU status word in AX without
D8 /4FSUB m32realSub m32real from ST(0) and s.r.in ST(0)
DC /4FSUB m64realSub m64real from ST(0) and s.r.in ST(0)
D8 E0+iFSUB ST(0),ST(i)Sub ST(i) from ST(0) and s.r.in ST(0)
DC E8+iFSUB ST(i),ST(0)Sub ST(0) from ST(i) and s.r.in ST(i)
DE E8+iFSUBP ST(i),ST(0)Sub ST(0) from ST(i), s.r.in ST(i) pop
DE E9FSUBPSub ST(0) from ST(1), s.r.in ST(1) pop
DA /4FISUB m32intSub m32int from ST(0) and s.r.in ST(0)
DE /4FISUB m16intSub m16int from ST(0) and s.r.in ST(0)
D8 /5FSUBR m32realSub ST(0) from m32real and s.r.in ST(0)
DC /5FSUBR m64realSub ST(0) from m64real and s.r.in ST(0)
D8 E8+iFSUBR ST(0),ST(i)Sub ST(0) from ST(i) and s.r.in ST(0)
DC E0+iFSUBR ST(i),ST(0)Sub ST(i) from ST(0) and s.r.in ST(i)
DE E0+iFSUBRP ST(i),ST(0)Sub ST(i) from ST(0), s.r. in ST(i) pop
DE E1FSUBRPSub ST(1) from ST(0), s.r.in ST(1) pop
DA /5FISUBR m32intSub ST(0) from m32int and s.r.in ST(0)
DE /5FISUBR m16intSub ST(0) from m16int and s.r.in ST(0)
D9 E4FTSTCompare ST(0) with 0.0
DD E0+iFUCOM ST(i)Compare ST(0) with ST(i)
DD E1FUCOMCompare ST(0) with ST(1)
DD E8+iFUCOMP ST(i)Compare ST(0) with ST(i) and pop
DD E9FUCOMPCompare ST(0) with ST(1) and pop
DA E9FUCOMPPCompare ST(0) with ST(1) and pop pop
D9 E5FXAMClassify value or number in ST(0)
D9 C8+iFXCH ST(i)Exchange ST(0) and ST(i)
D9 C9FXCHExchange ST(0) and ST(1)
D9 F4FXTRACTSeperate value in ST(0) exp. and sig.
D9 F1FYL2XReplace ST(1) with ST(1)*log2ST(0) and pop
D9 F9FYL2XP1Replace ST(1) with ST(1)*log2(ST(0)+1) pop
F4HLTHalt
F6 /7IDIV r/m8Divide
F7 /7IDIV r/m32Divide
F6 /5IMUL r/m8Multiply
F7 /5IMUL r/m32Multiply
0F AF /rIMUL r32,r/m32Multiply
6B /r ibIMUL r32,r/m32,imm8Multiply
6B /r ibIMUL r32,imm8Multiply
69 /r idIMUL r32,r/m32,imm32Multiply
69 /r idIMUL r32,imm32Multiply
E4 ibIN AL,imm8Input byte from imm8 I/O port address into AL
E5 ibIN EAX,imm8Input byte from imm8 I/O port address into EAX
ECIN AL,DXInput byte from I/O port in DX into AL
EDIN EAX,DXInput doubleword from I/O port in DX into EAX
FE /0INC r/m8Increment 1
FF /0INC r/m32Increment 1
40+rdINC r32Increment register by 1
6CINS m8Input byte from I/O(DX) into ES:(E)DI
6DINS m32Input dw from I/O(DX) into ES:(E)DI
CCINT 3Interrupt 3–trap to debugger
CD ibINT imm8Interrupt vector number (imm8)
CEINTOInterrupt 4–if overflow flag is 1
0F 08INVDFlush internal caches
0F 01 /7INVLPG mInvalidate TLB Entry for page (m)
CFIRETDInterrupt return(32)
77 cbJA rel8Jump short if above
73 cbJAE rel8Jump short if above or equal
76 cbJBE rel8Jump short if below or equal
72 cbJC rel8Jump short if carry
E3 cbJECXZ rel8Jump short if ECX register is 0
74 cbJE rel8Jump short if equal
7F cbJG rel8Jump short if greater
7D cbJGE rel8Jump short if greater or equal
7C cbJL rel8Jump short if less
7E cbJLE rel8Jump short if less or equal
75 cbJNE rel8Jump short if not equal
71 cbJNO rel8Jump short if not overflow
79 cbJNS rel8Jump short if not sign
70 cbJO rel8Jump short if overflow
7A cbJPE rel8Jump short if parity even
7B cbJPO rel8Jump short if parity odd
78 cbJS rel8Jump short if sign
0F 87 cdJA rel32Jump near if above
0F 83 cdJAE rel32Jump near if above or equal
0F 82 cdJB rel32Jump near if below
0F 86 cdJBE rel32Jump near if below or equal
0F 84 cdJE rel32Jump near if equal
0F 8F cdJG rel32Jump near if greater
0F 8D cdJGE rel32Jump near if greater or equal
0F 8C cdJL rel32Jump near if less
0F 8E cdJLE rel32Jump near if less or equal
0F 85 cdJNE rel32Jump near if not equal
0F 81 cdJNO rel32Jump near if not overflow
0F 89 cdJNS rel32Jump near if not sign
0F 80 cdJO rel32Jump near if overflow
0F 8A cdJPE rel32Jump near if parity even
0F 8B cdJPO rel32Jump near if parity odd
0F 88 cdJS rel32Jump near if sign
EB cbJMP rel8Jump short, relative,
E9 cdJMP rel32Jump near, relative,
FF /4JMP r/m32Jump near, abs.ind.in r/m32
EA cpJMP ptr16:32Jump far, abs.add given in operand
FF /rJMP m16:32Jump far, abs.ind.in m16:32
9FLAHFLoad Status Flags into AH
0F 02 /rLAR r32,r/m32Load Access Rights Byte
C5 /rLDS r32,m16:32Load DS:r32 with far ptr
8D /rLEA r32,mLoad effective address
C9LEAVESet ESP to EBP, then pop EBP
C4 /rLES r32,m16:32Load ES:r32 with far ptr
0F B4 /rLFS r32,m16:32Load FS:r32 with far ptr
0F B5 /rLGS r32,m16:32Load GS:r32 with far ptr
0F 01 /2LGDT m16&32Load m into GDTR
0F 01 /3LIDT m16&32Load m into IDTR
0F 00 /2LLDT r/m16Load segment selector r/m16 into LDTR
0F 01 /6LMSW r/m16Load r/m16 in machine status word of CR0
F0LOCKAsserts LOCK signal for duration ..
ACLODS m8Load byte at address DS:(E)SI into AL
ADLODS m32Load dword at address DS:(E)SI into EAX
E2 cbLOOP rel8Dec count;jump if count # 0
E1 cbLOOPE rel8Dec count;jump if count # 0 and ZF=1
E1 cbLOOPZ rel8Dec count;jump if count # 0 and ZF=1
E0 cbLOOPNE rel8Dec count;jump if count # 0 and ZF=0
E0 cbLOOPNZ rel8Dec count;jump if count # 0 and ZF=0
0F 03 /rLSL r16,r/m16Load Segment Limit
0F 03 /rLSL r32,r/m32Load Segment Limit
0F B2 /rLSS r32,m16:32Load SS:r32 with far ptr
0F 00 /3LTR r/m16Load Task Register
88 /rMOV r/m8,r8Move
89 /rMOV r/m32,r32Move
8A /rMOV r8,r/m8Move
8B /rMOV r32,r/m32Move
8C /rMOV r/m16,Sreg**Move segment register to r/m16
8E /rMOV Sreg,r/m16**Move r/m16 to segment register
A0MOV AL, moffs8*Move byte at ( seg:offset) to AL
A1MOV AX, moffs16*Move word at ( seg:offset) to AX
A1MOV EAX, moffs32*Move dword at ( seg:offset) to EAX
A2MOV moffs8*,ALMove AL to ( seg:offset)
A3MOV moffs16*,AXMove AX to ( seg:offset)
A3MOV moffs32*,EAXMove EAX to ( seg:offset)
B0+rbMOV r8,imm8Move imm8 to r8
B8+rdMOV r32,imm32Move imm32 to r32
C6 /0 ibMOV r/m8,imm8Move imm8 to r/m8
C7 /0 idMOV r/m32,imm32Move imm32 to r/m32
0F 22 /rMOV CR0, r32Move r32 to CR0
0F 22 /rMOV CR2, r32Move r32 to CR2
0F 22 /rMOV CR3, r32Move r32 to CR3
0F 22 /rMOV CR4, r32Move r32 to CR4
0F 20 /rMOV r32,CR0Move CR0 to r32
0F 20 /rMOV r32,CR2Move CR2 to r32
0F 20 /rMOV r32,CR3Move CR3 to r32
0F 20 /rMOV r32,CR4Move CR4 to r32
0F 21 /rMOV r32,DR0-DR7Move debug register to r32
0F 23 /rMOV DR0-DR7,r32Move r32 to debug register
0F 6E /rMOVD mm,r/m32Move doubleword from r/m32 to mm
0F 7E /rMOVD r/m32,mmMove doubleword from mm to r/m32
0F 6F /rMOVQ mm,mm/m64Move quadword from mm/m64 to mm
0F 7F /rMOVQ mm/m64,mmMove quadword from mm to mm/m64
A4MOVS m8,m8Move byte at DS:(E)SI to ES:(E)DI
A5MOVS m32,m32Move dword at DS:(E)SI to ES:(E)DI
0F BE /rMOVSX r32,r/m8Move byte to doubleword, sign-extension
0F BF /rMOVSX r32,r/m16Move word to doubleword, sign-extension
0F B6 /rMOVZX r32,r/m8Move byte to doubleword, zero-extension
0F B7 /rMOVZX r32,r/m16Move word to doubleword, zero-extension
F6 /4MUL r/m8Unsigned multiply
F7 /4MUL r/m32Unsigned multiply
F6 /3NEG r/m8Two’s complement negate r/m8
F7 /3NEG r/m32Two’s complement negate r/m32
90NOPNo operation
F6 /2NOT r/m8Reverse each bit of r/m8
F7 /2NOT r/m32Reverse each bit of r/m32
0C ibOR AL,imm8OR
0D idOR EAX,imm32OR
80 /1 ibOR r/m8,imm8OR
81 /1 idOR r/m32,imm32OR
83 /1 ibOR r/m32,imm8OR
08 /rOR r/m8,r8OR
09 /rOR r/m32,r32OR
0A /rOR r8,r/m8OR
0B /rOR r32,r/m32OR
E6 ibOUT imm8,ALOutput byte in AL to I/O(imm8)
E7 ibOUT imm8,EAXOutput dword in EAX to I/O(imm8)
EEOUT DX,ALOutput byte in AL to I/O(DX)
EFOUT DX,EAXOutput dword in EAX to I/O(DX)
6EOUTS DX,m8Output byte from DS:(E)SI to I/O(DX)
6FOUTS DX,m32Output dword from DS:(E)SI to I/O (DX)
0F 63 /rPACKSSWB mm,mm/m64Pack with Signed Saturation
0F 6B /rPACKSSDW mm,mm/m64Pack with Signed Saturation
0F 67 /rPACKUSWB mm,mm/m64Pack with Unsigned Saturation
0F FC /rPADDB mm,mm/m64Add packed bytes
0F FD /rPADDW mm,mm/m64Add packed words
0F FE /rPADDD mm,mm/m64Add packed dwords
0F EC /rPADDSB mm,mm/m64Add signed packed bytes
0F ED /rPADDSW mm,mm/m64Add signed packed words
0F DC /rPADDUSB mm,mm/m64Add unsigned pkd bytes
0F DD /rPADDUSW mm,mm/m64Add unsigned pkd words
0F DB /rPAND mm,mm/m64AND quadword from .. to ..
0F DF /rPANDN mm,mm/m64And qword from .. to NOT qw in mm
0F 74 /rPCMPEQB mm,mm/m64Packed Compare for Equal
0F 75 /rPCMPEQW mm,mm/m64Packed Compare for Equal
0F 76 /rPCMPEQD mm,mm/m64Packed Compare for Equal
0F 64 /rPCMPGTB mm,mm/m64Packed Compare for GT
0F 65 /rPCMPGTW mm,mm/m64Packed Compare for GT
0F 66 /rPCMPGTD mm,mm/m64Packed Compare for GT
0F F5 /rPMADDWD mm,mm/m64Packed Multiply and Add
0F E5 /rPMULHW mm,mm/m64Packed Multiply High
0F D5 /rPMULLW mm,mm/m64Packed Multiply Low
8F /0POP m32Pop m32
58+rdPOP r32Pop r32
1FPOP DSPop DS
07POP ESPop ES
17POP SSPop SS
0F A1POP FSPop FS
0F A9POP GSPop GS
61POPADPop EDI,… and EAX
9DPOPFDPop Stack into EFLAGS Register
0F EB /rPOR mm,mm/m64OR qword from .. to mm
0F F1 /rPSLLW mm,mm/m64Packed Shift Left Logical
0F 71 /6 ibPSLLW mm,imm8Packed Shift Left Logical
0F F2 /rPSLLD mm,mm/m64Packed Shift Left Logical
0F 72 /6 ibPSLLD mm,imm8Packed Shift Left Logical
0F F3 /rPSLLQ mm,mm/m64Packed Shift Left Logical
0F 73 /6 ibPSLLQ mm,imm8Packed Shift Left Logical
0F E1 /rPSRAW mm,mm/m64Packed Shift Right Arithmetic
0F 71 /4 ibPSRAW mm,imm8Packed Shift Right Arithmetic
0F E2 /rPSRAD mm,mm/m64Packed Shift Right Arithmetic
0F 72 /4 ibPSRAD mm,imm8Packed Shift Right Arithmetic
0F D1 /rPSRLW mm,mm/m64Packed Shift Right Logical
0F 71 /2 ibPSRLW mm,imm8Packed Shift Right Logical
0F D2 /rPSRLD mm,mm/m64Packed Shift Right Logical
0F 72 /2 ibPSRLD mm,imm8Packed Shift Right Logical
0F D3 /rPSRLQ mm,mm/m64Packed Shift Right Logical
0F 73 /2 ibPSRLQ mm,imm8Packed Shift Right Logical
0F F8 /rPSUBB mm,mm/m64Packed Subtract
0F F9 /rPSUBW mm,mm/m64Packed Subtract
0F FA /rPSUBD mm,mm/m64Packed Subtract
0F E8 /rPSUBSB mm,mm/m64Packed Subtract with Saturation
0F E9 /rPSUBSW mm,mm/m64Packed Subtract with Saturation
0F D8 /rPSUBUSB mm,mm/m64Packed Subtract Unsigned with S.
0F D9 /rPSUBUSW mm,mm/m64Packed Subtract Unsigned with S.
0F 68 /rPUNPCKHBW mm,mm/m64Unpack High Packed Data
0F 69 /rPUNPCKHWD mm,mm/m64Unpack High Packed Data
0F 6A /rPUNPCKHDQ mm,mm/m64Unpack High Packed Data
0F 60 /rPUNPCKLBW mm,mm/m64Unpack Low Packed Data
0F 61 /rPUNPCKLWD mm,mm/m64Unpack Low Packed Data
0F 62 /rPUNPCKLDQ mm,mm/m64Unpack Low Packed Data
FF /6PUSH r/m32Push r/m32
50+rdPUSH r32Push r32
6A ibPUSH imm8Push imm8
68 idPUSH imm32Push imm32
0EPUSH CSPush CS
16PUSH SSPush SS
1EPUSH DSPush DS
06PUSH ESPush ES
0F A0PUSH FSPush FS
0F A8PUSH GSPush GS
60PUSHADPush All g-regs
9CPUSHFDPush EFLAGS
0F EF /rPXOR mm,mm/m64XOR qword
D0 /2RCL r/m8,1Rotate 9 bits left once
D2 /2RCL r/m8,CLRotate 9 bits left CL times
C0 /2 ibRCL r/m8,imm8Rotate 9 bits left imm8 times
D1 /2RCL r/m32,1Rotate 33 bits left once
D3 /2RCL r/m32,CLRotate 33 bits left CL times
C1 /2 ibRCL r/m32,imm8Rotate 33 bits left imm8 times
D0 /3RCR r/m8,1Rotate 9 bits right once
D2 /3RCR r/m8,CLRotate 9 bits right CL times
C0 /3 ibRCR r/m8,imm8Rotate 9 bits right imm8 times
D1 /3RCR r/m32,1Rotate 33 bits right once
D3 /3RCR r/m32,CLRotate 33 bits right CL times
C1 /3 ibRCR r/m32,imm8Rotate 33 bits right imm8 times
D0 /0ROL r/m8,1Rotate 8 bits r/m8 left once
D2 /0ROL r/m8,CLRotate 8 bits r/m8 left CL times
C0 /0 ibROL r/m8,imm8Rotate 8 bits r/m8 left imm8 times
D1 /0ROL r/m32,1Rotate 32 bits r/m32 left once
D3 /0ROL r/m32,CLRotate 32 bits r/m32 left CL times
C1 /0 ibROL r/m32,imm8Rotate 32 bits r/m32 left imm8 times
D0 /1ROR r/m8,1Rotate 8 bits r/m8 right once
D2 /1ROR r/m8,CLRotate 8 bits r/m8 right CL times
C0 /1 ibROR r/m8,imm8Rotate 8 bits r/m16 right imm8 times
D1 /1ROR r/m32,1Rotate 32 bits r/m32 right once
D3 /1ROR r/m32,CLRotate 32 bits r/m32 right CL times
C1 /1 ibROR r/m32,imm8Rotate 32 bits r/m32 right imm8 times
0F 32RDMSRRead from Model Specific Register
0F 33RDPMCRead Performance-Monitoring counters
0F 31RDTSCRead Time-Stamp Counter
F3 6CREP INS m8,DXInput ECX bytes from port DX into ES:[(E)DI]
F3 6DREP INS m32,DXInput ECX dwords from port DX into ES:[(E)DI]
F3 A4REP MOVS m8,m8Move ECX bytes from DS:[(E)SI] to ES:[(E)DI]
F3 A5REP MOVS m32,m32Move ECX dwords from DS:[(E)SI] to ES:[(E)DI]
F3 6EREP OUTS DX,m8Output ECX bytes from DS:[(E)SI] to port DX
F3 6FREP OUTS DX,m32Output ECX dwords from DS:[(E)SI] to port DX
F3 ACREP LODS ALLoad ECX bytes from DS:[(E)SI] to AL
F3 ADREP LODS EAXLoad ECX dwords from DS:[(E)SI] to EAX
F3 AAREP STOS m8Fill ECX bytes at ES:[(E)DI] with AL
F3 ABREP STOS m32Fill ECX dwords at ES:[(E)DI] with EAX
F3 A6REPE CMPS m8,m8Find nonmatching bytes in m and m
F3 A7REPE CMPS m32,m32Find nonmatching dwords in m and m
F3 AEREPE SCAS m8Find non-AL byte starting at
F3 AFREPE SCAS m32Find non-EAX dword starting at
F2 A6REPNE CMPS m8,m8Find matching bytes in m and m
F2 A7REPNE CMPS m32,m32Find matching dwords in m and m
F2 AEREPNE SCAS m8Find AL, starting at ES:[(E)DI]
F2 AFREPNE SCAS m32Find EAX, starting at ES:[(E)DI]
C3RETNear return
CBRETFar return
C2 iwRET imm16Near return, pop imm16 bytes from stack
CA iwRET imm16Far return, pop imm16 bytes from stack
0F AARSMResume from System Management
9ESAHFStore AH into Flags
D0 /4SAL r/m8,1Shift Arithmetic Left
D2 /4SAL r/m8,CLShift Arithmetic Left
C0 /4 ibSAL r/m8,imm8Shift Arithmetic Left
D1 /4SAL r/m32,1Shift Arithmetic Left
D3 /4SAL r/m32,CLShift Arithmetic Left
C1 /4 ibSAL r/m32,imm8Shift Arithmetic Left
D0 /7SAR r/m8,1Shift Arithmetic Right
D2 /7SAR r/m8,CLShift Arithmetic Right
C0 /7 ibSAR r/m8,imm8Shift Arithmetic Right
D1 /7SAR r/m32,1Shift Arithmetic Right
D3 /7SAR r/m32,CLShift Arithmetic Right
C1 /7 ibSAR r/m32,imm8Shift Arithmetic Right
D0 /4SHL r/m8,1Shift Logical Left
D2 /4SHL r/m8,CLShift Logical Left
C0 /4 ibSHL r/m8,imm8Shift Logical Left
D1 /4SHL r/m32,1Shift Logical Left
D3 /4SHL r/m32,CLShift Logical Left
C1 /4 ibSHL r/m32,imm8Shift Logical Left
D0 /5SHR r/m8,1Shift Logical Right
D2 /5SHR r/m8,CLShift Logical Right
C0 /5 ibSHR r/m8,imm8Shift Logical Right
D1 /5SHR r/m32,1Shift Logical Right
D3 /5SHR r/m32,CLShift Logical Right
C1 /5 ibSHR r/m32,imm8Shift Logical Right
1C ibSBB AL,imm8Subtract with borrow
1D idSBB EAX,imm32Subtract with borrow
80 /3 ibSBB r/m8,imm8Subtract with borrow
81 /3 idSBB r/m32,imm32Subtract with borrow
83 /3 ibSBB r/m32,imm8Subtract with borrow
18 /rSBB r/m8,r8Subtract with borrow
19 /rSBB r/m32,r32Subtract with borrow
1A /rSBB r8,r/m8Subtract with borrow
1B /rSBB r32,r/m32Subtract with borrow
AESCAS m8Scan String
AFSCAS m32Scan String
0F 97 /rSETA r/m8Set byte if above
0F 93 /rSETAE r/m8Set byte if above or equal
0F 92 /rSETB r/m8Set byte if below
0F 96 /rSETBE r/m8Set byte if below or equal
0F 94 /rSETE r/m8Set byte if equal
0F 9F /rSETG r/m8Set byte if greater
0F 9D /rSETGE r/m8Set byte if greater or equal
0F 9C /rSETL r/m8Set byte if less
0F 9E /rSETLE r/m8Set byte if less or equal
0F 95 /rSETNE r/m8Set byte if not equal
0F 91 /rSETNO r/m8Set byte if not overflow
0F 99 /rSETNS r/m8Set byte if not sign
0F 90 /rSETO r/m8Set byte if overflow
0F 9A /rSETPE r/m8Set byte if parity even
0F 9B /rSETPO r/m8Set byte if parity odd
0F 98 /rSETS r/m8Set byte if sign
0F 01 /0SGDT mStore GDTR to m
0F 01 /1SIDT mStore IDTR to m
0F A4 /r ibSHLD r/m32,r32,imm8Double Precision Shift Left
0F A5 /rSHLD r/m32,r32,CLDouble Precision Shift Left
0F AC /r ibSHRD r/m32,r32,imm8Double Precision Shift Right
0F AD /rSHRD r/m32,r32,CLDouble Precision Shift Right
0F 00 /0SLDT r/m32Store Local Descriptor Table Register
0F 01 /4SMSW r/m32Store Machine Status Word
F9STCSet Carry Flag
FDSTDSet Direction Flag
FBSTISet Interrup Flag
AASTOS m8Store String
ABSTOS m32Store String
0F 00 /1STR r/m16Store Task Register
2C ibSUB AL,imm8Subtract
2D idSUB EAX,imm32Subtract
80 /5 ibSUB r/m8,imm8Subtract
81 /5 idSUB r/m32,imm32Subtract
83 /5 ibSUB r/m32,imm8Subtract
28 /rSUB r/m8,r8Subtract
29 /rSUB r/m32,r32Subtract
2A /rSUB r8,r/m8Subtract
2B /rSUB r32,r/m32Subtract
A8 ibTEST AL,imm8Logical Compare
A9 idTEST EAX,imm32Logical Compare
F6 /0 ibTEST r/m8,imm8Logical Compare
F7 /0 idTEST r/m32,imm32Logical Compare
84 /rTEST r/m8,r8Logical Compare
85 /rTEST r/m16,r16Logical Compare
85 /rTEST r/m32,r32Logical Compare
0F 0BUD2Undifined Instruction
0F 00 /4VERR r/m16Verify a Segment for Reading
0F 00 /5VERW r/m16Verify a Segment for Writing
9BWAITWait
9BFWAITWait
0F 09WBINVDWrite Back and Invalidate Cache
0F 30WRMSRWrite to Model Specific Register
0F C0 /rXADD r/m8,r8Exchange and Add
0F C1 /rXADD r/m16,r16Exchange and Add
0F C1 /rXADD r/m32,r32Exchange and Add
90+rdXCHG EAX,r32Exchange r32 with EAX
90+rdXCHG r32,EAXExchange EAX with r32
86 /rXCHG r/m8,r8Exchange byte
86 /rXCHG r8,r/m8Exchange byte
87 /rXCHG r/m32,r32Exchange doubleword
87 /rXCHG r32,r/m32Exchange doubleword
D7XLAT m8Table Look-up Translation
34 ibXOR AL,imm8Logical Exclusive OR
35 idXOR EAX,imm32Logical Exclusive OR
80 /6 ibXOR r/m8,imm8Logical Exclusive OR
81 /6 idXOR r/m32,imm32Logical Exclusive OR
83 /6 ibXOR r/m32,imm8Logical Exclusive OR
30 /rXOR r/m8,r8Logical Exclusive OR
31 /rXOR r/m32,r32Logical Exclusive OR
32 /rXOR r8,r/m8Logical Exclusive OR
33 /rXOR r32,r/m32Logical Exclusive OR

Opcode ordered Listing

Opcode,DataInstructionExplanation
00 /rADD r/m8,r8ADD
01 /rADD r/m32,r32ADD
02 /rADD r8,r/m8ADD
03 /rADD r32,r/m32ADD
04 ibADD AL,imm8Add
05 idADD EAX,imm32Add
06PUSH ESPush ES
07POP ESPop ES
08 /rOR r/m8,r8OR
09 /rOR r/m32,r32OR
0A /rOR r8,r/m8OR
0B /rOR r32,r/m32OR
0C ibOR AL,imm8OR
0D idOR EAX,imm32OR
0EPUSH CSPush CS
0F 00 /0SLDT r/m32Store Local Descriptor Table Register
0F 00 /1STR r/m16Store Task Register
0F 00 /2LLDT r/m16Load segment selector r/m16 into LDTR
0F 00 /3LTR r/m16Load Task Register
0F 00 /4VERR r/m16Verify a Segment for Reading
0F 00 /5VERW r/m16Verify a Segment for Writing
0F 01 /0SGDT mStore GDTR to m
0F 01 /1SIDT mStore IDTR to m
0F 01 /2LGDT m16&32Load m into GDTR
0F 01 /3LIDT m16&32Load m into IDTR
0F 01 /4SMSW r/m32Store Machine Status Word
0F 01 /6LMSW r/m16Load r/m16 in machine status word of CR0
0F 01 /7INVLPG mInvalidate TLB Entry for page (m)
0F 02 /rLAR r32,r/m32Load Access Rights Byte
0F 03 /rLSL r16,r/m16Load Segment Limit
0F 03 /rLSL r32,r/m32Load Segment Limit
0F 06CLTSClear Task-Switched Flag in Control Reg. Zero
0F 08INVDFlush internal caches
0F 09WBINVDWrite Back and Invalidate Cache
0F 0BUD2Undifined Instruction
0F 20 /rMOV r32,CR0Move CR0 to r32
0F 20 /rMOV r32,CR2Move CR2 to r32
0F 20 /rMOV r32,CR3Move CR3 to r32
0F 20 /rMOV r32,CR4Move CR4 to r32
0F 21 /rMOV r32,DR0-DR7Move debug register to r32
0F 22 /rMOV CR0, r32Move r32 to CR0
0F 22 /rMOV CR2, r32Move r32 to CR2
0F 22 /rMOV CR3, r32Move r32 to CR3
0F 22 /rMOV CR4, r32Move r32 to CR4
0F 23 /rMOV DR0-DR7,r32Move r32 to debug register
0F 30WRMSRWrite to Model Specific Register
0F 31RDTSCRead Time-Stamp Counter
0F 32RDMSRRead from Model Specific Register
0F 33RDPMCRead Performance-Monitoring counters
0F 40 /rCMOVO r32,r/m32Move if overflow
0F 41 /rCMOVNO r32,r/m32Move if not overflow
0F 42 /rCMOVB r32,r/m32Move if below
0F 42 /rCMOVC r32,r/m32Move if carry
0F 42 /rCMOVNAE r32,r/m32Move if not above or equal
0F 43 /rCMOVAE r32,r/m32Move if above or equal
0F 43 /rCMOVNB r32,r/m32Move if not below
0F 43 /rCMOVNC r32,r/m32Move if not carry
0F 44 /rCMOVE r32,r/m32Move if equal
0F 44 /rCMOVZ r32,r/m32Move if zero
0F 45 /rCMOVNE r32,r/m32Move if not equal
0F 45 /rCMOVNZ r32,r/m32Move if not zero
0F 46 /rCMOVBE r32,r/m32Move if below or equal
0F 46 /rCMOVNA r32,r/m32Move if not above
0F 47 /rCMOVA r32,r/m32Move if above
0F 47 /rCMOVNBE r32,r/m32Move if not below or equal
0F 48 /rCMOVS r32,r/m32Move if sign
0F 49 /rCMOVNS r32,r/m32Move if not sign
0F 4A /rCMOVP r32,r/m32Move if parity
0F 4A /rCMOVPE r32,r/m32Move if parity even
0F 4B /rCMOVNP r32,r/m32Move if not parity
0F 4B /rCMOVPO r32,r/m32Move if parity odd
0F 4C /rCMOVL r32,r/m32Move if less
0F 4C /rCMOVNGE r32,r/m32Move if not greater or equal
0F 4D /rCMOVGE r32,r/m32Move if greater or equal
0F 4D /rCMOVNL r32,r/m32Move if not less
0F 4E /rCMOVLE r32,r/m32Move if less or equal
0F 4E /rCMOVNG r32,r/m32Move if not greater
0F 4F /rCMOVG r32,r/m32Move if greater
0F 4F /rCMOVNLE r32,r/m32Move if not less or equal
0F 60 /rPUNPCKLBW mm,mm/m64Unpack Low Packed Data
0F 61 /rPUNPCKLWD mm,mm/m64Unpack Low Packed Data
0F 62 /rPUNPCKLDQ mm,mm/m64Unpack Low Packed Data
0F 63 /rPACKSSWB mm,mm/m64Pack with Signed Saturation
0F 64 /rPCMPGTB mm,mm/m64Packed Compare for GT
0F 65 /rPCMPGTW mm,mm/m64Packed Compare for GT
0F 66 /rPCMPGTD mm,mm/m64Packed Compare for GT
0F 67 /rPACKUSWB mm,mm/m64Pack with Unsigned Saturation
0F 68 /rPUNPCKHBW mm,mm/m64Unpack High Packed Data
0F 69 /rPUNPCKHWD mm,mm/m64Unpack High Packed Data
0F 6A /rPUNPCKHDQ mm,mm/m64Unpack High Packed Data
0F 6B /rPACKSSDW mm,mm/m64Pack with Signed Saturation
0F 6E /rMOVD mm,r/m32Move doubleword from r/m32 to mm
0F 6F /rMOVQ mm,mm/m64Move quadword from mm/m64 to mm
0F 71 /2 ibPSRLW mm,imm8Packed Shift Right Logical
0F 71 /4 ibPSRAW mm,imm8Packed Shift Right Arithmetic
0F 71 /6 ibPSLLW mm,imm8Packed Shift Left Logical
0F 72 /2 ibPSRLD mm,imm8Packed Shift Right Logical
0F 72 /4 ibPSRAD mm,imm8Packed Shift Right Arithmetic
0F 72 /6 ibPSLLD mm,imm8Packed Shift Left Logical
0F 73 /2 ibPSRLQ mm,imm8Packed Shift Right Logical
0F 73 /6 ibPSLLQ mm,imm8Packed Shift Left Logical
0F 74 /rPCMPEQB mm,mm/m64Packed Compare for Equal
0F 75 /rPCMPEQW mm,mm/m64Packed Compare for Equal
0F 76 /rPCMPEQD mm,mm/m64Packed Compare for Equal
0F 77EMMSSet the FP tag word to empty
0F 7E /rMOVD r/m32,mmMove doubleword from mm to r/m32
0F 7F /rMOVQ mm/m64,mmMove quadword from mm to mm/m64
0F 80 cdJO rel32Jump near if overflow
0F 81 cdJNO rel32Jump near if not overflow
0F 82 cdJB rel32Jump near if below
0F 83 cdJAE rel32Jump near if above or equal
0F 84 cdJE rel32Jump near if equal
0F 85 cdJNE rel32Jump near if not equal
0F 86 cdJBE rel32Jump near if below or equal
0F 87 cdJA rel32Jump near if above
0F 88 cdJS rel32Jump near if sign
0F 89 cdJNS rel32Jump near if not sign
0F 8A cdJPE rel32Jump near if parity even
0F 8B cdJPO rel32Jump near if parity odd
0F 8C cdJL rel32Jump near if less
0F 8D cdJGE rel32Jump near if greater or equal
0F 8E cdJLE rel32Jump near if less or equal
0F 8F cdJG rel32Jump near if greater
0F 90 /rSETO r/m8Set byte if overflow
0F 91 /rSETNO r/m8Set byte if not overflow
0F 92 /rSETB r/m8Set byte if below
0F 93 /rSETAE r/m8Set byte if above or equal
0F 94 /rSETE r/m8Set byte if equal
0F 95 /rSETNE r/m8Set byte if not equal
0F 96 /rSETBE r/m8Set byte if below or equal
0F 97 /rSETA r/m8Set byte if above
0F 98 /rSETS r/m8Set byte if sign
0F 99 /rSETNS r/m8Set byte if not sign
0F 9A /rSETPE r/m8Set byte if parity even
0F 9B /rSETPO r/m8Set byte if parity odd
0F 9C /rSETL r/m8Set byte if less
0F 9D /rSETGE r/m8Set byte if greater or equal
0F 9E /rSETLE r/m8Set byte if less or equal
0F 9F /rSETG r/m8Set byte if greater
0F A0PUSH FSPush FS
0F A1POP FSPop FS
0F A2CPUIDEAX := Processor id.info.
0F A3 /rBT r/m32,r32Bit Test
0F A4 /r ibSHLD r/m32,r32,imm8Double Precision Shift Left
0F A5 /rSHLD r/m32,r32,CLDouble Precision Shift Left
0F A8PUSH GSPush GS
0F A9POP GSPop GS
0F AARSMResume from System Management
0F AB /rBTS r/m32,r32Bit Test and Set
0F AC /r ibSHRD r/m32,r32,imm8Double Precision Shift Right
0F AD /rSHRD r/m32,r32,CLDouble Precision Shift Right
0F AF /rIMUL r32,r/m32Multiply
0F B0 /rCMPXCHG r/m8,r8Compare and Exchange
0F B1 /rCMPXCHG r/m32,r32Compare and Exchange
0F B2 /rLSS r32,m16:32Load SS:r32 with far ptr
0F B3 /rBTR r/m32,r32Bit Test and Clear
0F B4 /rLFS r32,m16:32Load FS:r32 with far ptr
0F B5 /rLGS r32,m16:32Load GS:r32 with far ptr
0F B6 /rMOVZX r32,r/m8Move byte to doubleword, zero-extension
0F B7 /rMOVZX r32,r/m16Move word to doubleword, zero-extension
0F BA /4 ibBT r/m32,imm8Bit Test
0F BA /5 ibBTS r/m32,imm8Bit Test and Set
0F BA /6 ibBTR r/m32,imm8Bit Test and Clear
0F BA /7 ibBTC r/m32,imm8Bit Test and Complement
0F BB /rBTC r/m32,r32Bit Test and Complement
0F BC /rBSF r32,r/m32Bit scan forward on r/m32
0F BD /rBSR r32,r/m32Bit scan reverse on r/m32
0F BE /rMOVSX r32,r/m8Move byte to doubleword, sign-extension
0F BF /rMOVSX r32,r/m16Move word to doubleword, sign-extension
0F C0 /rXADD r/m8,r8Exchange and Add
0F C1 /rXADD r/m16,r16Exchange and Add
0F C1 /rXADD r/m32,r32Exchange and Add
0F C7 /1 m64CMPXCHG8B m64Compare and Exchange
0F C8+rdBSWAP r32Reverses the byte order of a r32
0F D1 /rPSRLW mm,mm/m64Packed Shift Right Logical
0F D2 /rPSRLD mm,mm/m64Packed Shift Right Logical
0F D3 /rPSRLQ mm,mm/m64Packed Shift Right Logical
0F D5 /rPMULLW mm,mm/m64Packed Multiply Low
0F D8 /rPSUBUSB mm,mm/m64Packed Subtract Unsigned with S.
0F D9 /rPSUBUSW mm,mm/m64Packed Subtract Unsigned with S.
0F DB /rPAND mm,mm/m64AND quadword from .. to ..
0F DC /rPADDUSB mm,mm/m64Add unsigned pkd bytes
0F DD /rPADDUSW mm,mm/m64Add unsigned pkd words
0F DF /rPANDN mm,mm/m64And qword from .. to NOT qw in mm
0F E1 /rPSRAW mm,mm/m64Packed Shift Right Arithmetic
0F E2 /rPSRAD mm,mm/m64Packed Shift Right Arithmetic
0F E5 /rPMULHW mm,mm/m64Packed Multiply High
0F E8 /rPSUBSB mm,mm/m64Packed Subtract with Saturation
0F E9 /rPSUBSW mm,mm/m64Packed Subtract with Saturation
0F EB /rPOR mm,mm/m64OR qword from .. to mm
0F EC /rPADDSB mm,mm/m64Add signed packed bytes
0F ED /rPADDSW mm,mm/m64Add signed packed words
0F EF /rPXOR mm,mm/m64XOR qword
0F F1 /rPSLLW mm,mm/m64Packed Shift Left Logical
0F F2 /rPSLLD mm,mm/m64Packed Shift Left Logical
0F F3 /rPSLLQ mm,mm/m64Packed Shift Left Logical
0F F5 /rPMADDWD mm,mm/m64Packed Multiply and Add
0F F8 /rPSUBB mm,mm/m64Packed Subtract
0F F9 /rPSUBW mm,mm/m64Packed Subtract
0F FA /rPSUBD mm,mm/m64Packed Subtract
0F FC /rPADDB mm,mm/m64Add packed bytes
0F FD /rPADDW mm,mm/m64Add packed words
0F FE /rPADDD mm,mm/m64Add packed dwords
10 /rADC r/m8,r8Add with carry
11 /rADC r/m32,r32Add with carry
12 /rADC r8,r/m8Add with carry
13 /rADC r32,r/m32Add with carry
14 ibADC AL,imm8Add with carry
15 idADC EAX,imm32Add with carry
16PUSH SSPush SS
17POP SSPop SS
18 /rSBB r/m8,r8Subtract with borrow
19 /rSBB r/m32,r32Subtract with borrow
1A /rSBB r8,r/m8Subtract with borrow
1B /rSBB r32,r/m32Subtract with borrow
1C ibSBB AL,imm8Subtract with borrow
1D idSBB EAX,imm32Subtract with borrow
1EPUSH DSPush DS
1FPOP DSPop DS
20 /rAND r/m8,r8AND
21 /rAND r/m32,r32AND
22 /rAND r8,r/m8AND
23 /rAND r32,r/m32AND
24 ibAND AL,imm8AND
25 idAND EAX,imm32AND
26ES:Segment overide prefix
27DAADecimal adjust AL after addition
28 /rSUB r/m8,r8Subtract
29 /rSUB r/m32,r32Subtract
2A /rSUB r8,r/m8Subtract
2B /rSUB r32,r/m32Subtract
2C ibSUB AL,imm8Subtract
2D idSUB EAX,imm32Subtract
2ECS:Segment overide prefix
2FDASDecimal adjust AL after subtraction
30 /rXOR r/m8,r8Logical Exclusive OR
31 /rXOR r/m32,r32Logical Exclusive OR
32 /rXOR r8,r/m8Logical Exclusive OR
33 /rXOR r32,r/m32Logical Exclusive OR
34 ibXOR AL,imm8Logical Exclusive OR
35 idXOR EAX,imm32Logical Exclusive OR
36SS:Segment overide prefix
37AAAASCII adjust AL after addition
38 /rCMP r/m8,r8Compare
39 /rCMP r/m32,r32Compare
3A /rCMP r8,r/m8Compare
3B /rCMP r32,r/m32Compare
3C ibCMP AL,imm8Compare
3D idCMP EAX,imm32Compare
3EDS:Segment overide prefix
3FAASASCII adjust AL after subtraction
40+rdINC r32Increment register by 1
48+rdDEC r32Decrement r32 by 1
50+rdPUSH r32Push r32
58+rdPOP r32Pop r32
60PUSHADPush All g-regs
61POPADPop EDI,… and EAX
62 /rBOUND r32,m32&32Check Array Index Against Bounds
63 /rARPL r/m16,r16Adjust Request Privilege Level of Sel.
64FS:Segment overide prefix
65GS:Segment overide prefix
66Opsize:Operand size overide prefix
67Address:Address size overide prefix
68 idPUSH imm32Push imm32
69 /r idIMUL r32,imm32Multiply
69 /r idIMUL r32,r/m32,imm32Multiply
6A ibPUSH imm8Push imm8
6B /r ibIMUL r32,imm8Multiply
6B /r ibIMUL r32,r/m32,imm8Multiply
6CINS m8Input byte from I/O(DX) into ES:(E)DI
6DINS m32Input dw from I/O(DX) into ES:(E)DI
6EOUTS DX,m8Output byte from DS:(E)SI to I/O(DX)
6FOUTS DX,m32Output dword from DS:(E)SI to I/O (DX)
70 cbJO rel8Jump short if overflow
71 cbJNO rel8Jump short if not overflow
72 cbJC rel8Jump short if carry
73 cbJAE rel8Jump short if above or equal
74 cbJE rel8Jump short if equal
75 cbJNE rel8Jump short if not equal
76 cbJBE rel8Jump short if below or equal
77 cbJA rel8Jump short if above
78 cbJS rel8Jump short if sign
79 cbJNS rel8Jump short if not sign
7A cbJPE rel8Jump short if parity even
7B cbJPO rel8Jump short if parity odd
7C cbJL rel8Jump short if less
7D cbJGE rel8Jump short if greater or equal
7E cbJLE rel8Jump short if less or equal
7F cbJG rel8Jump short if greater
80 /0 ibADD r/m8,imm8Add
80 /1 ibOR r/m8,imm8OR
80 /2 ibADC r/m8,imm8Add with carry
80 /3 ibSBB r/m8,imm8Subtract with borrow
80 /4 ibAND r/m8,imm8AND
80 /5 ibSUB r/m8,imm8Subtract
80 /6 ibXOR r/m8,imm8Logical Exclusive OR
80 /7 ibCMP r/m8,imm8Compare
81 /0 idADD r/m32,imm32Add
81 /1 idOR r/m32,imm32OR
81 /2 idADC r/m32,imm32Add with carry
81 /3 idSBB r/m32,imm32Subtract with borrow
81 /4 idAND r/m32,imm32AND
81 /5 idSUB r/m32,imm32Subtract
81 /6 idXOR r/m32,imm32Logical Exclusive OR
81 /7 idCMP r/m32,imm32Compare
83 /0 ibADD r/m32,imm8Add
83 /1 ibOR r/m32,imm8OR
83 /2 ibADC r/m32,imm8Add with carry
83 /3 ibSBB r/m32,imm8Subtract with borrow
83 /4 ibAND r/m32,imm8AND
83 /5 ibSUB r/m32,imm8Subtract
83 /6 ibXOR r/m32,imm8Logical Exclusive OR
83 /7 ibCMP r/m32,imm8Compare
84 /rTEST r/m8,r8Logical Compare
85 /rTEST r/m16,r16Logical Compare
85 /rTEST r/m32,r32Logical Compare
86 /rXCHG r/m8,r8Exchange byte
86 /rXCHG r8,r/m8Exchange byte
87 /rXCHG r/m32,r32Exchange doubleword
87 /rXCHG r32,r/m32Exchange doubleword
88 /rMOV r/m8,r8Move
89 /rMOV r/m32,r32Move
8A /rMOV r8,r/m8Move
8B /rMOV r32,r/m32Move
8C /rMOV r/m16,Sreg**Move segment register to r/m16
8D /rLEA r32,mLoad effective address
8E /rMOV Sreg,r/m16**Move r/m16 to segment register
8F /0POP m32Pop m32
90NOPNo operation
90+rdXCHG EAX,r32Exchange r32 with EAX
90+rdXCHG r32,EAXExchange EAX with r32
98CBWConvert Byte to Word
99CDQConvert Doubleword to Quadword
99CWDConvert Word to Doubleword
9A cpCALL ptr16:32Call far, abs.add. given in operand
9BFWAITWait
9BWAITWait
9B D9 /6FSTENV m14/28byteStore FPU environment
9B D9 /7FSTCW m2byteStore FPU control word
9B DB E2FCLEXClear f.e.f. after checking for ..
9B DB E3FINITInitialize FPU after …
9B DD /6FSAVE m94/108byteStore FPU status to m94 or m108
9B DD /7FSTSW m2byteStore FPU status word at m2byte after
9B DF E0FSTSW AXStore FPU status word in AX after
9CPUSHFDPush EFLAGS
9DPOPFDPop Stack into EFLAGS Register
9ESAHFStore AH into Flags
9FLAHFLoad Status Flags into AH
A0MOV AL, moffs8*Move byte at ( seg:offset) to AL
A1MOV AX, moffs16*Move word at ( seg:offset) to AX
A1MOV EAX, moffs32*Move dword at ( seg:offset) to EAX
A2MOV moffs8*,ALMove AL to ( seg:offset)
A3MOV moffs16*,AXMove AX to ( seg:offset)
A3MOV moffs32*,EAXMove EAX to ( seg:offset)
A4MOVS m8,m8Move byte at DS:(E)SI to ES:(E)DI
A5MOVS m32,m32Move dword at DS:(E)SI to ES:(E)DI
A6CMPSBCompare byte at DS:(E)SI with ES:(E)DI
A7CMPSDCompare dw at DS:(E)SI with ES:(E)DI
A8 ibTEST AL,imm8Logical Compare
A9 idTEST EAX,imm32Logical Compare
AASTOS m8Store String
ABSTOS m32Store String
ACLODS m8Load byte at address DS:(E)SI into AL
ADLODS m32Load dword at address DS:(E)SI into EAX
AESCAS m8Scan String
AFSCAS m32Scan String
B0+rbMOV r8,imm8Move imm8 to r8
B8+rdMOV r32,imm32Move imm32 to r32
C0 /0 ibROL r/m8,imm8Rotate 8 bits r/m8 left imm8 times
C0 /1 ibROR r/m8,imm8Rotate 8 bits r/m16 right imm8 times
C0 /2 ibRCL r/m8,imm8Rotate 9 bits left imm8 times
C0 /3 ibRCR r/m8,imm8Rotate 9 bits right imm8 times
C0 /4 ibSAL r/m8,imm8Shift Arithmetic Left
C0 /4 ibSHL r/m8,imm8Shift Logical Left
C0 /5 ibSHR r/m8,imm8Shift Logical Right
C0 /7 ibSAR r/m8,imm8Shift Arithmetic Right
C1 /0 ibROL r/m32,imm8Rotate 32 bits r/m32 left imm8 times
C1 /1 ibROR r/m32,imm8Rotate 32 bits r/m32 right imm8 times
C1 /2 ibRCL r/m32,imm8Rotate 33 bits left imm8 times
C1 /3 ibRCR r/m32,imm8Rotate 33 bits right imm8 times
C1 /4 ibSAL r/m32,imm8Shift Arithmetic Left
C1 /4 ibSHL r/m32,imm8Shift Logical Left
C1 /5 ibSHR r/m32,imm8Shift Logical Right
C1 /7 ibSAR r/m32,imm8Shift Arithmetic Right
C2 iwRET imm16Near return, pop imm16 bytes from stack
C3RETNear return
C4 /rLES r32,m16:32Load ES:r32 with far ptr
C5 /rLDS r32,m16:32Load DS:r32 with far ptr
C6 /0 ibMOV r/m8,imm8Move imm8 to r/m8
C7 /0 idMOV r/m32,imm32Move imm32 to r/m32
C8 iw 00ENTER imm16,0Create a stack frame for a procedure
C8 iw 01ENTER imm16,1Create a nested stack frame for a proc.
C8 iw ibENTER imm16,imm8Create a nested stack frame for a proc.
C9LEAVESet ESP to EBP, then pop EBP
CA iwRET imm16Far return, pop imm16 bytes from stack
CBRETFar return
CCINT 3Interrupt 3–trap to debugger
CD ibINT imm8Interrupt vector number (imm8)
CEINTOInterrupt 4–if overflow flag is 1
CFIRETDInterrupt return(32)
D0 /0ROL r/m8,1Rotate 8 bits r/m8 left once
D0 /1ROR r/m8,1Rotate 8 bits r/m8 right once
D0 /2RCL r/m8,1Rotate 9 bits left once
D0 /3RCR r/m8,1Rotate 9 bits right once
D0 /4SAL r/m8,1Shift Arithmetic Left
D0 /4SHL r/m8,1Shift Logical Left
D0 /5SHR r/m8,1Shift Logical Right
D0 /7SAR r/m8,1Shift Arithmetic Right
D1 /0ROL r/m32,1Rotate 32 bits r/m32 left once
D1 /1ROR r/m32,1Rotate 32 bits r/m32 right once
D1 /2RCL r/m32,1Rotate 33 bits left once
D1 /3RCR r/m32,1Rotate 33 bits right once
D1 /4SAL r/m32,1Shift Arithmetic Left
D1 /4SHL r/m32,1Shift Logical Left
D1 /5SHR r/m32,1Shift Logical Right
D1 /7SAR r/m32,1Shift Arithmetic Right
D2 /0ROL r/m8,CLRotate 8 bits r/m8 left CL times
D2 /1ROR r/m8,CLRotate 8 bits r/m8 right CL times
D2 /2RCL r/m8,CLRotate 9 bits left CL times
D2 /3RCR r/m8,CLRotate 9 bits right CL times
D2 /4SAL r/m8,CLShift Arithmetic Left
D2 /4SHL r/m8,CLShift Logical Left
D2 /5SHR r/m8,CLShift Logical Right
D2 /7SAR r/m8,CLShift Arithmetic Right
D3 /0ROL r/m32,CLRotate 32 bits r/m32 left CL times
D3 /1ROR r/m32,CLRotate 32 bits r/m32 right CL times
D3 /2RCL r/m32,CLRotate 33 bits left CL times
D3 /3RCR r/m32,CLRotate 33 bits right CL times
D3 /4SAL r/m32,CLShift Arithmetic Left
D3 /4SHL r/m32,CLShift Logical Left
D3 /5SHR r/m32,CLShift Logical Right
D3 /7SAR r/m32,CLShift Arithmetic Right
D4 0AAAMASCII adjust AX after multiplication
D5 0AAADASCII adjust AX before division
D6SETALCSet ALC: undocumented
D7XLAT m8Table Look-up Translation
D8 /0FADD m32realAdd m32real to ST(0) and s.r. in ST(0)
D8 /1FMUL m32realMultiply ST(0) by m32real and s.r.in ST(0)
D8 /2FCOM m32realCompare ST(0) with m32real.
D8 /3FCOMP m32realCompare ST(0) with m32real,pop r.stack.
D8 /4FSUB m32realSub m32real from ST(0) and s.r.in ST(0)
D8 /5FSUBR m32realSub ST(0) from m32real and s.r.in ST(0)
D8 /6FDIV m32realDivide ST(0) by m32real and s.r.in ST(0)
D8 /7FDIVR m32realDivide m32real by ST(0) and s.r.in ST(0)
D8 C0+iFADD ST(0),ST(i)Add ST(0) to ST(i) and s.r.in ST(0)
D8 C8+iFMUL ST(0),ST(i)Multiply ST(0) by ST(i) and s.r.in ST(0)
D8 D0+iFCOM ST(i)Compare ST(0) with ST(i).
D8 D1FCOMCompare ST(0) with ST(1).
D8 D8+iFCOMP ST(i)Compare ST(0) with ST(i), pop
D8 D9FCOMPCompare ST(0) with ST(1), pop
D8 E0+iFSUB ST(0),ST(i)Sub ST(i) from ST(0) and s.r.in ST(0)
D8 E8+iFSUBR ST(0),ST(i)Sub ST(0) from ST(i) and s.r.in ST(0)
D8 F0+iFDIV ST(0),ST(i)Divide ST(0) by ST(i) and s.r.in ST(0)
D8 F8+iFDIVR ST(0),ST(i)Divide ST(i) by ST(0) and s.r.in ST(0)
D9 /0FLD m32realPush m32real
D9 /2FST m32realCopy ST(0) to m32real
D9 /3FSTP m32realCopy ST(0) to m32real and pop
D9 /4FLDENV m14/28byteLoad FPU environment from m14/m28
D9 /5FLDCW m2byteLoad FPU control word from m2byte
D9 /6FNSTENV m14/28byteStore FPU env without
D9 /7FNSTCW m2byteStore FPU control word without
D9 C0+iFLD ST(i)Push ST(i)
D9 C8+iFXCH ST(i)Exchange ST(0) and ST(i)
D9 C9FXCHExchange ST(0) and ST(1)
D9 D0FNOPNo operation is performed
D9 E0FCHSComplements sign of ST(0)
D9 E1FABSReplace ST(0) with its absolute value
D9 E4FTSTCompare ST(0) with 0.0
D9 E5FXAMClassify value or number in ST(0)
D9 E8FLD1Push +1.0
D9 E9FLDL2TPush log2 10
D9 EAFLDL2EPush log2 e
D9 EBFLDPIPush pi
D9 ECFLDLG2Push log10 2
D9 EDFLDLN2Push loge 2
D9 EEFLDZPush +0.0
D9 F0F2XM1Replace ST(0) with 2**ST(0) - 1
D9 F1FYL2XReplace ST(1) with ST(1)*log2ST(0) and pop
D9 F2FPTANReplaces ST(0) with its tangent push 1.0
D9 F3FPATANRepalces ST(1) with arctan(ST(1)/ST(0)) pop
D9 F4FXTRACTSeperate value in ST(0) exp. and sig.
D9 F5FPREM1Replaces ST(0) with IEEE rem(ST(0)/ST(1))
D9 F6FDECSTPDecrement TOP field in FPU status word.
D9 F7FINCSTPIncrement the TOP field FPU status r.
D9 F8FPREMReplaces ST(0) with rem (ST(0)/ST(1))
D9 F9FYL2XP1Replace ST(1) with ST(1)*log2(ST(0)+1) pop
D9 FAFSQRTsquare root of ST(0)
D9 FBFSINCOSCompute sine and consine of ST(0) s push c
D9 FCFRNDINTRound ST(0) to an integer
D9 FDFSCALEScale ST(0) by ST(1)
D9 FEFSINReplace ST(0) with its sine
D9 FFFCOSReplace ST(0) with its cosine
DA /0FIADD m32intAdd m32int to ST(0) and s.r.in ST(0)
DA /1FIMUL m32intMultiply ST(0) by m32int and s.r.in ST(0)
DA /2FICOM m32intCompare ST(0) with m32int
DA /3FICOMP m32intCompare ST(0) with m32int and pop
DA /4FISUB m32intSub m32int from ST(0) and s.r.in ST(0)
DA /5FISUBR m32intSub ST(0) from m32int and s.r.in ST(0)
DA /6FIDIV m32intDivide ST(0) by m32int and s.r.in ST(0)
DA /7FIDIVR m32intDivide m32int by ST(0) and s.r.in ST(0)
DA C0+iFCMOVB ST(0),ST(i)Move if below
DA C8+iFCMOVE ST(0),ST(i)Move if equal
DA D0+iFCMOVBE ST(0),ST(i)Move if below or equal
DA D8+iFCMOVU ST(0),ST(i)Move if unordered
DA E9FUCOMPPCompare ST(0) with ST(1) and pop pop
DB /0FILD m32intPush m32int
DB /2FIST m32intStore ST(0) in m32int
DB /3FISTP m32intStore ST(0) in m32int and pop
DB /5FLD m80realPush m80real
DB /7FSTP m80realCopy ST(0) to m80real and pop
DB C0+iFCMOVNB ST(0),ST(i)Move if not below
DB C8+iFCMOVNE ST(0),ST(i)Move if not equal
DB D0+iFCMOVNBE ST(0),ST(i)Move if not below or equal
DB D8+iFCMOVNU ST(0),ST(i)Move if not unordered
DB E2FNCLEXClear f.e.f. without checking for ..
DB E3FNINITInitialize FPU without …
DB E8+iFUCOMI ST,ST(i)Compare ST(0) with ST(i), check o.v.set s.f.
DB F0+iFCOMI ST,ST(i)Compare ST(0) with ST(i), set status flags
DC /0FADD m64realAdd m64real to ST(0) and s.r.in ST(0)
DC /1FMUL m64realMultiply ST(0) by m64real and s.r.in ST(0)
DC /2FCOM m64realCompare ST(0) with m64real.
DC /3FCOMP m64realCompare ST(0) with m64real,pop r.stack.
DC /4FSUB m64realSub m64real from ST(0) and s.r.in ST(0)
DC /5FSUBR m64realSub ST(0) from m64real and s.r.in ST(0)
DC /6FDIV m64realDivide ST(0) by m64real and s.r.in ST(0)
DC /7FDIVR m64realDivide m64real by ST(0) and s.r.in ST(0)
DC C0+iFADD ST(i),ST(0)Add ST(i) to ST(0) and s.r. in ST(i)
DC C8+iFMUL ST(i),ST(0)Multiply ST(i) by ST(0) and s.r.in ST(i)
DC E0+iFSUBR ST(i),ST(0)Sub ST(i) from ST(0) and s.r.in ST(i)
DC E8+iFSUB ST(i),ST(0)Sub ST(0) from ST(i) and s.r.in ST(i)
DC F0+iFDIVR ST(i),ST(0)Divide ST(0) by ST(i) and s.r.in ST(i)
DC F8+iFDIV ST(i),ST(0)Divide ST(i) by ST(0) and s.r.in ST(i)
DD /0FLD m64realPush m64real
DD /2FST m64realCopy ST(0) to m64real
DD /3FSTP m64realCopy ST(0) to m64real and pop
DD /4FRSTOR m94/108byteLoad FPU status from m94 or m108 byte
DD /6FNSAVE m94/108byteStore FPU environment to m94 or m108
DD /7FNSTSW m2byteStore FPU status word at m2byte without
DD C0+iFFREE ST(i)Sets tag for ST(i) to empty
DD D0+iFST ST(i)Copy ST(0) to ST(i)
DD D8+iFSTP ST(i)Copy ST(0) to ST(i) and pop
DD E0+iFUCOM ST(i)Compare ST(0) with ST(i)
DD E1FUCOMCompare ST(0) with ST(1)
DD E8+iFUCOMP ST(i)Compare ST(0) with ST(i) and pop
DD E9FUCOMPCompare ST(0) with ST(1) and pop
DE /0FIADD m16intAdd m16int to ST(0) and s.r.in ST(0)
DE /1FIMUL m16intMultiply ST(0) by m16int and s.r.in ST(0)
DE /2FICOM m16intCompare ST(0) with m16int
DE /3FICOMP m16intCompare ST(0) with m16int and pop
DE /4FISUB m16intSub m16int from ST(0) and s.r.in ST(0)
DE /5FISUBR m16intSub ST(0) from m16int and s.r.in ST(0)
DE /6FIDIV m16intDivide ST(0) by m64int and s.r.in ST(0)
DE /7FIDIVR m16intDivide m64int by ST(0) and s.r.in ST(0)
DE C0+iFADDP ST(i),ST(0)Add ST(0) to ST(i), s.r.in ST(i),pop r.stack
DE C1FADDPAdd ST(0) to ST(1), s.r.in ST(1),pop r.stack
DE C8+iFMULP ST(i),ST(0)Multiply ST(i) by ST(0), s.r.in ST(i) pop
DE C9FMULPMultiply ST(1) by ST(0), s.r.in ST(1) pop
DE D9FCOMPPCompare ST(0) with ST(1), pop pop
DE E0+iFSUBRP ST(i),ST(0)Sub ST(i) from ST(0), s.r. in ST(i) pop
DE E1FSUBRPSub ST(1) from ST(0), s.r.in ST(1) pop
DE E8+iFSUBP ST(i),ST(0)Sub ST(0) from ST(i), s.r.in ST(i) pop
DE E9FSUBPSub ST(0) from ST(1), s.r.in ST(1) pop
DE F0+iFDIVRP ST(i),ST(0)Divide ST(0) by ST(i), s.r.in ST(i) pop
DE F1FDIVRPDivide ST(0) by ST(1), s.r.in ST(1) pop
DE F8+iFDIVP ST(i),ST(0)Divide ST(i) by ST(0), s.r.in ST(i) pop
DE F9FDIVPDivide ST(1) by ST(0), s.r.in ST(1) pop
DF /0FILD m16intPush m16int
DF /2FIST m16intStore ST(0) in m16int
DF /3FISTP m16intStore ST(0) in m16int and pop
DF /4FBLD m80bcdConvert m80BCD to real and push
DF /5FILD m64intPush m64int
DF /6FBSTP m80bcdStore ST(0) in m80bcd and pop ST(0)
DF /7FISTP m64intStore ST(0) in m64int and pop
DF E0FNSTSW AXStore FPU status word in AX without
DF E8+iFUCOMIP ST,ST(i)Compare ST(0) with ST(i), check ovssf pop
DF F0+iFCOMIP ST,ST(i)Compare ST(0) with ST(i), set s.f. ,pop
E0 cbLOOPNE rel8Dec count;jump if count # 0 and ZF=0
E0 cbLOOPNZ rel8Dec count;jump if count # 0 and ZF=0
E1 cbLOOPE rel8Dec count;jump if count # 0 and ZF=1
E1 cbLOOPZ rel8Dec count;jump if count # 0 and ZF=1
E2 cbLOOP rel8Dec count;jump if count # 0
E3 cbJECXZ rel8Jump short if ECX register is 0
E4 ibIN AL,imm8Input byte from imm8 I/O port address into AL
E5 ibIN EAX,imm8Input byte from imm8 I/O port address into EAX
E6 ibOUT imm8,ALOutput byte in AL to I/O(imm8)
E7 ibOUT imm8,EAXOutput dword in EAX to I/O(imm8)
E8 cdCALL rel32Call near, rel to n.inst
E9 cdJMP rel32Jump near, relative,
EA cpJMP ptr16:32Jump far, abs.add given in operand
EB cbJMP rel8Jump short, relative,
ECIN AL,DXInput byte from I/O port in DX into AL
EDIN EAX,DXInput doubleword from I/O port in DX into EAX
EEOUT DX,ALOutput byte in AL to I/O(DX)
EFOUT DX,EAXOutput dword in EAX to I/O(DX)
F0LOCKAsserts LOCK signal for duration ..
F1INT1ICEBP
F2 A6REPNE CMPS m8,m8Find matching bytes in m and m
F2 A7REPNE CMPS m32,m32Find matching dwords in m and m
F2 AEREPNE SCAS m8Find AL, starting at ES:[(E)DI]
F2 AFREPNE SCAS m32Find EAX, starting at ES:[(E)DI]
F3 6CREP INS m8,DXInput ECX bytes from port DX into ES:[(E)DI]
F3 6DREP INS m32,DXInput ECX dwords from port DX into ES:[(E)DI]
F3 6EREP OUTS DX,m8Output ECX bytes from DS:[(E)SI] to port DX
F3 6FREP OUTS DX,m32Output ECX dwords from DS:[(E)SI] to port DX
F3 A4REP MOVS m8,m8Move ECX bytes from DS:[(E)SI] to ES:[(E)DI]
F3 A5REP MOVS m32,m32Move ECX dwords from DS:[(E)SI] to ES:[(E)DI]
F3 A6REPE CMPS m8,m8Find nonmatching bytes in m and m
F3 A7REPE CMPS m32,m32Find nonmatching dwords in m and m
F3 AAREP STOS m8Fill ECX bytes at ES:[(E)DI] with AL
F3 ABREP STOS m32Fill ECX dwords at ES:[(E)DI] with EAX
F3 ACREP LODS ALLoad ECX bytes from DS:[(E)SI] to AL
F3 ADREP LODS EAXLoad ECX dwords from DS:[(E)SI] to EAX
F3 AEREPE SCAS m8Find non-AL byte starting at
F3 AFREPE SCAS m32Find non-EAX dword starting at
F4HLTHalt
F5CMCComplement CF flag
F6 /2NOT r/m8Reverse each bit of r/m8
F6 /3NEG r/m8Two’s complement negate r/m8
F6 /4MUL r/m8Unsigned multiply
F6 /5IMUL r/m8Multiply
F6 /6DIV r/m8Unsigned divide AX by r/m8
F6 /7IDIV r/m8Divide
F6 /0 ibTEST r/m8,imm8Logical Compare
F7 /2NOT r/m32Reverse each bit of r/m32
F7 /3NEG r/m32Two’s complement negate r/m32
F7 /4MUL r/m32Unsigned multiply
F7 /5IMUL r/m32Multiply
F7 /6DIV r/m16Unsigned divide DX:AX by r/m16
F7 /6DIV r/m32Unsigned divide EDX:EAX by r/m32
F7 /7IDIV r/m32Divide
F7 /0 idTEST r/m32,imm32Logical Compare
F8CLCClear CF flag
F9STCSet Carry Flag
FACLIClear interrupt flag
FBSTISet Interrup Flag
FCCLDClear DF flag
FDSTDSet Direction Flag
FE /0INC r/m8Increment 1
FE /1DEC r/m8Decrement r/m8 by 1
FF /0INC r/m32Increment 1
FF /1DEC r/m32Decrement r/m32 by 1
FF /2CALL r/m32Call near, abs.ind.add. given in r/m32
FF /3CALL m16:32Call far, abs.ind.add. given in m16:32
FF /4JMP r/m32Jump near, abs.ind.in r/m32
FF /6PUSH r/m32Push r/m32
FF /rJMP m16:32Jump far, abs.ind.in m16:32